TRACK CONCATENATOR J GENERATOR
An error correction system according to claim 3, wherein the second shift register of each pair of said shift registers includes a modulo two addition circuit at the input to the first b stages of said shift register and at the input to the stages having a corresponding term in the generator polynomial ĥ.
An error correction system according to claim 2, wherein the first shift register of each pair of said shift registers includes a modulo two addition circuit for each stage of said register and a feedback connection from the output means from each stage of said register to said respective modulo two addition circuit to perform the modulo two addition of successive incoming bits of the bytes.Ĥ. An error correction system according to claim 1, wherein each pair of shift registers operates in parallel on the bits of bytes of respective portions of said binary message defined by its respective submatrix, said pairs of shift registers operating on its respective portions in unison.ģ. An error correction system for correcting up to b-adjacent errors in a b-bit byte of a byte-oriented binary message comprising:Ģ. The byte in error is located by loading the subsequent syndrome bytes of the partition in error into the corresponding shift register and shifting until the contents match the first non-zero syndrome byte, the number of shifts being indicative of the byte in error.ġ. The partition in error is determined by detecting the first non-zero syndrome byte. Likewise, a pair of shift registers are associated with each partition of the information so that the partial syndrome byte outputs can be modulo 2 added with the respective check bits to obtain the syndrome byte. The partial check bytes from the respective pairs of shift registers are modulo 2 added to obtain the check byte. Each pair of shift registers operates on the bits of a byte in parallel and the shift registers in each partition operate in unison. Each partitioned portion of the message is operated on by a pair of shift registers to generate the check byte contribution of the respective partition.
H (2b +c) ,b where r = kb= c and 0 ≤ c < r. Each of the submatrices are concatenated iteratively by b so that the matrix H can be designated by submatrices H r,b H (r -b), b H (r -2b) ,b. The information is encoded by attaching a plurality of check bytes in accordance with an H matrix consisting of a predetermined number of submatrices, each of which operates on distinct partitioned portions of the message bytes. An error correcting system is provided for a parallel track or parallel channel information handling system in which the information is divided into blocks of bytes of b-bits each.
0 kommentar(er)
